11.10.2021 | Research
Current research at DSC: Early estimation of power consumption of neural networks on GPUs
When developing AI systems for the Internet of Things, early estimation of power consumption is important. A new method allows system engineers to determine the consumption at an early stage.
In the paper “Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs
”, our research associate Christopher Metz in cooperation with Mehran Goli (DFKI) developed an approach to estimate the power consumption of GPGPUs when executing Convolutional Neural Networks (CNNs), in early phases of development.
In their study, the authors provide first results on their method presented in the previous paper “Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs
” (we reported »here
). They managed to predict the power consumption with an absolute error of up to less than 1%. The best result was obtained for a RESNET variation with an absolute error of 0.73%. This compares to the worst result with an absolute error of 15.75% for the Densenet201. This results in an average absolute error of 8.3%. The large variation can be attributed to an unbalanced training data set. This contains more variations of the RESNET than for the Densenet. To improve the results, the authors are working on optimizing the training data set.
To estimate the power consumption, they trained a simple neural network. The neural network receives the instructions that the GPGPU executes as well as important hardware components of the GPGPU as input. The output of the neural network is the power consumption. One aim is to integrate the completed model into a compiler extension so that system designers in the future can determine the power consumption of artificial neural networks at an early stage. This could make the selection process more cost effective and environmentally friendly in the future.
The work was done in cooperation with the Cyber-Physical Systems group of DFKI at Bremen and was submitted and presented at the International Conference on Hardware/Software Codesign and System Synthesis
). Further authors are Dr.-Ing. Mehran Goli (DFKI/University of Bremen) and Prof. Rolf Drechsler (University of Bremen/DFKI).
The International Conference on Hardware/Software Codesign and System Synthesis
(CODES+ISSS) is the premier event in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern Embedded Systems, Cyber-Physical Systems (CPS), and Internet-of-Things (IoT), from system-level specification and optimization to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.
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